Modeling RF MOSFETs after electrical stress using low-noise microstrip line layout

完整後設資料紀錄

DC 欄位	值	語言
dc.contributor.author	Kao, HL	en_US
dc.contributor.author	Chin, A	en_US
dc.contributor.author	Lai, JM	en_US
dc.contributor.author	Lee, CF	en_US
dc.contributor.author	Chiang, KC	en_US
dc.contributor.author	McAlister, SP	en_US
dc.date.accessioned	2014-12-08T15:25:25Z	-
dc.date.available	2014-12-08T15:25:25Z	-
dc.date.issued	2005	en_US
dc.identifier.isbn	0-7803-8983-2	en_US
dc.identifier.issn	1529-2517	en_US
dc.identifier.uri	http://hdl.handle.net/11536/17813	-
dc.description.abstract	A novel microstrip line layout is developed to direct measure the min. noise figure (NFmin) accurately instead of the complicated de-embedding procedure in conventional CPW line. Very low NFmin of 1.05 dB at 10 GHz is directly measured in 16 gate fingers 0.18 mu m MOSFETs without any de-embedding. Based on the accurate NFmin measurement, we have developed the self-consistent DC, S-parameters and NFmin model to predict device characteristics after the continuous stress with good accuracy.	en_US
dc.language.iso	en_US	en_US
dc.subject	NFmin	en_US
dc.subject	RF noise	en_US
dc.subject	lifetime	en_US
dc.subject	stress	en_US
dc.subject	model	en_US
dc.title	Modeling RF MOSFETs after electrical stress using low-noise microstrip line layout	en_US
dc.type	Proceedings Paper	en_US
dc.identifier.journal	2005 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, Digest of Papers	en_US
dc.citation.spage	157	en_US
dc.citation.epage	160	en_US
dc.contributor.department	電子工程學系及電子研究所	zh_TW
dc.contributor.department	Department of Electronics Engineering and Institute of Electronics	en_US
dc.identifier.wosnumber	WOS:000230541500035	-
顯示於類別：	會議論文