標題: A low-power H.264/AVC decoder
作者: Lin, TA
Liu, TM
Lee, CY
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
公開日期: 2005
摘要: In this paper, we can save memory access in inter and intra prediction by adopting the proposed memory-efficient decoding ordering. In our proposed hierarchical syntax parser, gated clock technique can be effectively applied to reduce power. Simulation shows the proposed design consumes 88mW in real time decoding 1080HD video sequence.
URI: http://hdl.handle.net/11536/17817
ISBN: 0-7803-9060-1
期刊: 2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation & Test (VLSI-TSA-DAT), Proceedings of Technical Papers
起始頁: 283
結束頁: 286
顯示於類別:會議論文