標題: | Run-time reconfiguration scheduling of 3D-rendering on a reconfigurable system |
作者: | Chiang, Kuen-Cheng Lee, Meng-Tho Shann, Jean Jyh-Jiun Chung, Chung-Ping 資訊工程學系 Department of Computer Science |
關鍵字: | 3D rendering;reconfigurable computing;hardware scheduling;processing element;system-on-a-chip |
公開日期: | 2005 |
摘要: | With the dramatically increasing demands for multimedia processing capabilities in portable electronic devices, the architectural supports for various multimedia computations in one platform are crucial to the success of a product. Although application-specific accelerators have performance advantages, their inflexibilities seriously impede the applicability and shorten product lifetime. On the other hand, a general-purpose processor has benefits to wide applicability but can not meet the real-time criteria in many cases. Therefore, we develop a platform consisting of a general-purpose CPU, an array of processing elements, and a shared memory to transfer data between them. In addition, we propose two scheduling methods, First-Come-First-Serve and Priority, to process the 3D models with a better performance. Experimental results indicate that the priority scheduling significantly improves the 3D-rendering in both computation speed and silicon area, compared with FCFS scheduling. Given the same speed requirements on both FCFS and priority scheduling methods, the priority scheduling requires only 75% of the silicon area. On the other hand, it yields 30% to 80% speedup with the same area. Moreover, with priority scheduling, its performance advantage can be further increased by skills such as partial reconfiguration and multi-context configuration, to reduce its reconfiguration overhead. |
URI: | http://hdl.handle.net/11536/17842 |
ISBN: | 978-980-6560-46-8 |
期刊: | 3RD INTERNATIONAL CONFERENCE ON COMPUTING, COMMUNICATIONS AND CONTROL TECHNOLOGIES, VOL 1, PROCEEDINGS |
起始頁: | 30 |
結束頁: | 35 |
Appears in Collections: | Conferences Paper |