Low temperature polycrystalline silicon thin film transistors fabricated by amorphous silicon spacer structure with pre-patterned TEOS oxide layer

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DC 欄位	值	語言
dc.contributor.author	Cheng, Huang-Chung	en_US
dc.contributor.author	Tsai, Chun-Chien	en_US
dc.contributor.author	Lu, Jian-Hao	en_US
dc.contributor.author	Chang, Ting-Kuo	en_US
dc.contributor.author	Lin, Ching-Wei	en_US
dc.contributor.author	Chen, Bo-Ting	en_US
dc.date.accessioned	2014-12-08T15:25:29Z	-
dc.date.available	2014-12-08T15:25:29Z	-
dc.date.issued	2005	en_US
dc.identifier.isbn	978-957-28522-2-4	en_US
dc.identifier.uri	http://hdl.handle.net/11536/17889	-
dc.description.abstract	In this paper, location-controlled grain growth with a-Si spacer structure was fabricated. Consequently, High-performance poly-Si TFTs with field-effect mobility exceeding 367 cm(2)/V-s and high device uniformity have been fabricated. The excellent electrical characteristics is attributed to large grain and grain boundary elimination in the channel region.	en_US
dc.language.iso	en_US	en_US
dc.title	Low temperature polycrystalline silicon thin film transistors fabricated by amorphous silicon spacer structure with pre-patterned TEOS oxide layer	en_US
dc.type	Proceedings Paper	en_US
dc.identifier.journal	IDMC 05: PROCEEDINGS OF THE INTERNATIONAL DISPLAY MANUFACTURING CONFERENCE 2005	en_US
dc.citation.spage	52	en_US
dc.citation.epage	54	en_US
dc.contributor.department	電子工程學系及電子研究所	zh_TW
dc.contributor.department	Department of Electronics Engineering and Institute of Electronics	en_US
dc.identifier.wosnumber	WOS:000259399200012	-
顯示於類別：	會議論文