An efficient hierarchical motion estimation on algorithm and its VLSI architecture

Abstract

This manuscript addresses the design and implementation of an efficient hierarchical motion estimation algorithm, HMEA, using multiple motion vector candidates to increase the estimation quality. HMEA satisfies the high estimation performance and efficient VLSI implementation. The algorithm adopts multi-resolution frames to reduce the computation complexity, and the original frame is down sampled into one-fourth and one-sixteenth respectively. At the smallest resolution, the least two motion vector candidates are selected using full-search block matching algorithm with search range equals to 4. At the middle level, these two motion vector candidates are used as center points for local searches, and the search range is reduce to 2. Then, at the original resolution level, the final motion vector is obtained from local search around the single candidate from the middle level. This paper also describes an efficient VLSI architecture based on the HMEA. We implement this architecture with about 59K gates and 798 bytes of RAM for a search range of [-16.0, +15.5] by using a synthesizable VHDL.