Design to avoid the over-gate-driven effect on ESD protection circuits in deep-submicron CMOS processes

Abstract

Although the gate-driven (or gate-coupled) technique was reported to improve ESD robustness of NMOS devices, the over-gate-driven effect has been found to degrade ESD level. This effect makes the gate-driven technique hard to be well optimized in deep-submicron CMOS ICs. In this work, a new design is proposed to overcome such over-gate-driven effect by circuit design and to achieve the maximum ESD capability of devices. The experimental results have shown significant improvement on the machine-model (MM) ESD robustness of ESD protection circuit by this new proposed design. This new design is portable (process-migration) for applications in different CMOS processes without modifying the process step or mask layer.