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dc.contributor.authorLin, YWen_US
dc.contributor.authorLee, CYen_US
dc.date.accessioned2014-12-08T15:25:52Z-
dc.date.available2014-12-08T15:25:52Z-
dc.date.issued2004en_US
dc.identifier.isbn0-7803-8660-4en_US
dc.identifier.urihttp://hdl.handle.net/11536/18311-
dc.description.abstractA new FFT processor with radix-8 algorithm and novel matrix buffer is presented in this paper. About 64 K bit memory can be saved in 8 K-point FFT by new dynamic scaling approach. Moreover, with data scheduling and prefetched buffering, single-port memory can be adopted in our FFT processor. A test chip for 8 K mode DVB-T system has been designed and fabricated using 0.18 mu m CMOS process with core area of 4.84mm(2) and consumes only 25.2 mW at 20 MHz.en_US
dc.language.isoen_USen_US
dc.titleA new dynamic scaling FFT processoren_US
dc.typeProceedings Paperen_US
dc.identifier.journalPROCEEDINGS OF THE 2004 IEEE ASIA-PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS, VOL 1 AND 2: SOC DESIGN FOR UBIQUITOUS INFORMATION TECHNOLOGYen_US
dc.citation.spage449en_US
dc.citation.epage452en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000227668700113-
Appears in Collections:Conferences Paper