A low power and high speed viterbi decoder chip for WLAN applications

Abstract

This paper presents a 166Mb/s, 64-state, radix-4, 16-level soft decison Viterbi decoder for high speed WLAN applications. With the path merging and trace forward techniques, the memory read operations are reduced to save power cunsumption. A test chip is fabricated in 0.35 mum 1P4M CMOS process, and can achieve the maximum throughout rate of 166Mbit/s under 3.3V The measured power consumption is below 55mW under 66M6/s throughput rate at 2.2V.