標題: Digital background calibration technique for pipelined analog-to-digital converters
作者: Liu, HC
Lee, ZM
Wu, JT
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
公開日期: 2003
摘要: A new background calibration technique for pipelined analog-to-digital converters is proposed. By dividing the step sizes of the multiplying digital-to-analog converter (MDAC) in a pipeline stages and injecting a random signal into the MDAC, it is possible to calibrate a pipeline stage without interrupting the normal analog-to-digital operation. The calibration can eliminate the nonlinear effects due to the MDAC's gain error, input offset voltage, and output errors in the digital-to-analog conversion.
URI: http://hdl.handle.net/11536/18639
ISBN: 0-7803-7761-3
期刊: PROCEEDINGS OF THE 2003 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL I: ANALOG CIRCUITS AND SIGNAL PROCESSING
起始頁: 881
結束頁: 884
Appears in Collections:Conferences Paper