標題: | Novel ESD implantation for sub-quarter-micron CMOS technology with enhanced machine-model ESD robustness |
作者: | Ker, MD Hsu, HC Peng, JH 電機學院 College of Electrical and Computer Engineering |
公開日期: | 2002 |
摘要: | A novel ESD implantation method is proposed to significantly improve machine-model (MM) electrostatic discharge (ESD) robustness of CMOS integrated circuits in sub-quarter-micron CMOS processes. By using this method, the ESD current is discharged far away from the surface channel of NMOS, therefore the NMOS can sustain a much higher ESD level, especially under the machine-model ESD stress. The MM ESD robustness of the gate-grounded NMOS (ggNMOS) with a device dimension of W/L = 300mum/0.5mum has been successfully improved from the original 450V to become 675V in a 0.25-mum CMOS process. |
URI: | http://hdl.handle.net/11536/18879 |
ISBN: | 0-7803-7416-9 |
期刊: | PROCEEDINGS OF THE 9TH INTERNATIONAL SYMPOSIUM ON THE PHYSICAL & FAILURE ANALYSIS OF INTEGRATED CIRCUITS |
起始頁: | 70 |
結束頁: | 74 |
顯示於類別: | 會議論文 |