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dc.contributor.authorHsu, CCen_US
dc.contributor.authorWu, JTen_US
dc.date.accessioned2014-12-08T15:26:36Z-
dc.date.available2014-12-08T15:26:36Z-
dc.date.issued2002en_US
dc.identifier.isbn0-7803-7363-4en_US
dc.identifier.urihttp://hdl.handle.net/11536/18901-
dc.description.abstractA high-speed high-resolution sample-and-hold amplifier (SHA) is designed for time-interleaved analog-to-digital converter applications. Using the techniques of pre-charging and output capacitor coupling can mitigate the requirements for the opamp, resulting in low power dissipation. Implemented in a standard 0.25 mum CMOS technology, the SHA achieves 73 dB SFDR for 2 Vpp input at 100 MHz sampling rate. The performance is not degraded for input's frequency up to the Nyquist frequency. Power consumption is 33 mW from a single 2.5 V supply.en_US
dc.language.isoen_USen_US
dc.titleA 33-mW 12-bit 100-MHz sample-and-hold amplifieren_US
dc.typeProceedings Paperen_US
dc.identifier.journal2002 IEEE ASIA-PACIFIC CONFERENCE ON ASIC PROCEEDINGSen_US
dc.citation.spage169en_US
dc.citation.epage172en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000180272700043-
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