標題: On-chip ESD protection circuit design with novel substrate-triggered SCR device in sub-quarter-micron CMOS process
作者: Ker, MD
Hsu, KC
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
公開日期: 2002
摘要: A novel design concept to turn on the SCR device by applying the substrate-triggered method is first proposed in the literature for effective on-chip ESD protection design. To avoid the, transient-induced latch-up issue, the substrate-triggered SCR devices are stacked in the ESD protection circuits. The turn-on efficiency of SCR can be greatly improved by applying the substrate-triggered method. The on-chip ESD protection circuits designed with the substrate-triggered SCR devices for input pad, output pad, and power pad have been successfully verified in a 0.25-mum CMOS process. The substrate-triggered SCR device with a smaller layout area of only 40mumx20mum can sustain the HBM ESD stress of higher than 7kV.
URI: http://hdl.handle.net/11536/18921
ISBN: 0-7803-7448-7
期刊: 2002 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL V, PROCEEDINGS
起始頁: 529
結束頁: 532
Appears in Collections:Conferences Paper