CDM ESD Protection in CMOS Integrated Circuits

Abstract

The impacts of charged-device-model (CDM) electrostatic discharge (ESD) events on integrated circuit (IC,) products are presented in this paper. The mechanism of chip-level CDM ESD event is introduced with some case studies on CDM ESD damages. Besides the chip-level CDM ESD event, the board-level CDM ESD event, which had been reported to cause damages in many customer-returned ICs, is also investigated in this work The chip-level and board-level CDM ESD levels of several test devices and test circuits fabricated in CMOS processes are characterized and compared. The experimental results have shown that the board-level CDM ESD level of the test circuit is much lower than the chip-level CDM ESD level, which indicates that the board-level CDM ESD test is more critical than the chip-level CDM ESD test in the field applications. In addition, failure analysis reveals that the failure on the test circuit under board-level CDM ESD test is much severer than that under chip-level CDM ESD test.