標題: Thermal stability of PVD TiN gate and its impacts on characteristics of CMOS transistors
作者: Wang, MF
Kao, YC
Huang, TY
Lin, HC
Chang, CY
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
公開日期: 2001
摘要: The effects of rapid-thermal annealing (RTA) after source/drain (S/D) implant on the characteristics of CMOS transistors with sputtered TiN gate were investigated. Our results indicate that n(+)/p junctions need higher thermal budget than p(+)/n junctions to achieve low leakage performance. It was also found fron C-V measurements that the flat-band voltage and oxide thickness are both affected by the annealing treatment, especially for p-channel devices. A hump in the subthreshold characteristics of p-channel transistors is observed, owing to the existence of a leakage path along the isolation edge. It is also shown that agglomeration phenomenon is easier to incur during the high-temperature RTA step as the metal gate width becomes narrower. When this happens, gate oxide integrity would be degraded, resulting in increased gate leakage of n-channel transistors.
URI: http://hdl.handle.net/11536/19143
ISBN: 0-9651577-5-X
期刊: 2001 6TH INTERNATIONAL SYMPOSIUM ON PLASMA- AND PROCESS-INDUCED DAMAGE
起始頁: 36
結束頁: 39
Appears in Collections:Conferences Paper