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dc.contributor.authorChen, TYen_US
dc.contributor.authorKer, MDen_US
dc.date.accessioned2014-12-08T15:26:55Z-
dc.date.available2014-12-08T15:26:55Z-
dc.date.issued2001en_US
dc.identifier.isbn0-7803-6412-0en_US
dc.identifier.urihttp://hdl.handle.net/11536/19157-
dc.description.abstractThe operation principles of gate-driven design and substrate-triggered design for ESD (ElectroStatic Discharge) protection are first explained by energy-band diagrams in this paper. The on-chip ESD protection devices realized in 0.18-mum and 0.35-mum CMOS processes are used to verify the efficiency of gate-driven or substrate-triggered designs. The substrate-triggered design can effectively and continually improve ESD robustness of protection devices than the gate-driven design. The HEM (Human-Body-Model) ESD level of NMOS with a W/L of 300 mum/0.3 mum can be improved from the original 0.8kV to become 3.3kV by the substrate-triggered design. But, the gate-driven design cannot continually improve the ESD level of the same device in the subquarter-micron CMOS process.en_US
dc.language.isoen_USen_US
dc.titleESD protection strategy for sub-quarter-micron CMOS technology: Gate-driven design versus substrate-triggered designen_US
dc.typeProceedings Paperen_US
dc.identifier.journal2001 INTERNATIONAL SYMPOSIUM ON VLSI TECHNOLOGY, SYSTEMS, AND APPLICATIONS, PROCEEDINGS OF TECHNICAL PAPERSen_US
dc.citation.spage232en_US
dc.citation.epage235en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000169941100059-
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