完整後設資料紀錄
DC 欄位語言
dc.contributor.authorKer, MDen_US
dc.contributor.authorLo, WYen_US
dc.contributor.authorChang, HHen_US
dc.date.accessioned2014-12-08T15:27:05Z-
dc.date.available2014-12-08T15:27:05Z-
dc.date.issued2000en_US
dc.identifier.urihttp://hdl.handle.net/11536/19305-
dc.description.abstractA new diode string design with very low leakage current is proposed for using in the on-chip power supply ESD electrostatic discharge) clamp circuits. Three traditional designs of the stacked diode strings used in the power supply ESD clamp circuits are also fabricated in the same test chip to verify the improvement of this new design. By adding an NMOS-controlled lateral SCR (NCLSCR) device into the stacked diode string, the leakage current of this new proposed diode string with 6 stacked diodes under a 5-V (3.3-V) forward bias condition can be controlled below 2.1 (1.07) nA at an environment temperature of 125 degrees C. The blocking voltage of this new diode string design with NCLSCR can be linearly adjusted by simply changing the number of the stacked diodes in the diode string for application across the power lines with different voltage levels to achieve the whole-chip ESD protection scheme.en_US
dc.language.isoen_USen_US
dc.titleNew diode string design with very low leakage current for using in power supply ESD clamp circuitsen_US
dc.typeProceedings Paperen_US
dc.identifier.journalISCAS 2000: IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS - PROCEEDINGS, VOL V: EMERGING TECHNOLOGIES FOR THE 21ST CENTURYen_US
dc.citation.spage69en_US
dc.citation.epage72en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000088845800018-
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