A CMOS rms-to-dc converter using Delta Sigma multiplier-divider

Abstract

A novel topology for CMOS Delta Sigma rms-to-dc converters is described. Analysis shows that the proposed topology is insensitive to most circuit imperfections except offset voltages. A test circuit of a 1st-order single-ended rms-to-dc converter is realized in a 0.8 mu m double-poly CMOS process. Experimental results demonstrate that input waveforms with crest factors as high as 3 can be measured at the 800mV full-scale input level. It provides a maximum relative error of +/-1% of reading.