完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Tarntair, FG | en_US |
dc.contributor.author | Wang, CC | en_US |
dc.contributor.author | Hong, WK | en_US |
dc.contributor.author | Huang, HK | en_US |
dc.contributor.author | Cheng, HC | en_US |
dc.date.accessioned | 2014-12-08T15:27:14Z | - |
dc.date.available | 2014-12-08T15:27:14Z | - |
dc.date.issued | 1998 | en_US |
dc.identifier.isbn | 1-55899-415-7 | en_US |
dc.identifier.issn | 0272-9172 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/19460 | - |
dc.description.abstract | A triode structure of chimney-shaped field emitter arrays is proposed in this article. This triode structure includes the chimney-shaped emitter, thermal oxidation dioxide, and the plateau-shaped singlecrystalline silicon gate electrode. For the application of the matrix-addressable and large area flat panel display, the uniform structure of the emitters and the yield become critical manufacturing issues when attempting to control nano-meter size features. The uniformity and yield of the chimney-shaped emitters are very well controlled. The nano-sized gate-to-emitter separations can be created by the changing thickness of the insulator. The uniformity of the insulator and emitter material can be controlled within 3% which can be obtained by most large area thin film deposition tools, not by photolithography. | en_US |
dc.language.iso | en_US | en_US |
dc.title | Chimney-shaped and plateau-shaped gate electrode field emission arrays | en_US |
dc.type | Proceedings Paper | en_US |
dc.identifier.journal | MATERIALS ISSUES IN VACUUM MICROELECTRONICS | en_US |
dc.citation.volume | 509 | en_US |
dc.citation.spage | 15 | en_US |
dc.citation.epage | 20 | en_US |
dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
dc.identifier.wosnumber | WOS:000077248500028 | - |
顯示於類別: | 會議論文 |