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dc.contributor.authorLu, CWen_US
dc.contributor.authorLee, CLen_US
dc.contributor.authorChen, JEen_US
dc.contributor.authorSu, CCen_US
dc.date.accessioned2014-12-08T15:27:20Z-
dc.date.available2014-12-08T15:27:20Z-
dc.date.issued1998en_US
dc.identifier.isbn0-8186-9191-3en_US
dc.identifier.urihttp://hdl.handle.net/11536/19586-
dc.description.abstractIn this work, a new IDDQ methodology, which is very suitable for testing deep submicron digital ULSI CMOS ICs, is proposed and demonstrated. It incorporates three new BICSs and has advantages of reduction in the circuit partitioning number, low input voltage, high resolution, low power supply voltage, and improved fault detectability and diagnosability.en_US
dc.language.isoen_USen_US
dc.titleA new IDDQ testing scheme employing charge storage BICS circuit for deep submicron CMOS ULSIen_US
dc.typeProceedings Paperen_US
dc.identifier.journal1998 IEEE INTERNATIONAL WORKSHOP ON IDDQ TESTING, PROCEEDINGSen_US
dc.citation.spage54en_US
dc.citation.epage58en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000077911200010-
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