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dc.contributor.authorLiang, HCen_US
dc.contributor.authorLee, CLen_US
dc.contributor.authorChen, JEen_US
dc.date.accessioned2014-12-08T15:27:35Z-
dc.date.available2014-12-08T15:27:35Z-
dc.date.issued1996en_US
dc.identifier.isbn0-8186-7478-4en_US
dc.identifier.urihttp://hdl.handle.net/11536/19837-
dc.language.isoen_USen_US
dc.titleInvalid state identification for sequential circuit test generationen_US
dc.typeProceedings Paperen_US
dc.identifier.journalPROCEEDINGS OF THE FIFTH ASIAN TEST SYMPOSIUM (ATS '96)en_US
dc.citation.spage10en_US
dc.citation.epage15en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:A1996BG49W00003-
Appears in Collections:Conferences Paper