Invalid state identification for sequential circuit test generation

完整後設資料紀錄

DC 欄位	值	語言
dc.contributor.author	Liang, HC	en_US
dc.contributor.author	Lee, CL	en_US
dc.contributor.author	Chen, JE	en_US
dc.date.accessioned	2014-12-08T15:27:35Z	-
dc.date.available	2014-12-08T15:27:35Z	-
dc.date.issued	1996	en_US
dc.identifier.isbn	0-8186-7478-4	en_US
dc.identifier.uri	http://hdl.handle.net/11536/19837	-
dc.language.iso	en_US	en_US
dc.title	Invalid state identification for sequential circuit test generation	en_US
dc.type	Proceedings Paper	en_US
dc.identifier.journal	PROCEEDINGS OF THE FIFTH ASIAN TEST SYMPOSIUM (ATS '96)	en_US
dc.citation.spage	10	en_US
dc.citation.epage	15	en_US
dc.contributor.department	電子工程學系及電子研究所	zh_TW
dc.contributor.department	Department of Electronics Engineering and Institute of Electronics	en_US
dc.identifier.wosnumber	WOS:A1996BG49W00003	-
顯示於類別：	會議論文