| 標題: | TECHNOLOGY MAPPING FOR FPGA USING GENERALIZED FUNCTIONAL DECOMPOSITION |
| 作者: | WANG, KH HWANG, TT CHEN, C 資訊工程學系 Department of Computer Science |
| 公開日期: | 1993 |
| URI: | http://hdl.handle.net/11536/20233 |
| ISBN: | 7-80003-275-6 |
| 期刊: | NEW ADVANCES IN COMPUTER AIDED DESIGN & COMPUTER GRAPHICS, VOLS 1 AND 2 |
| 起始頁: | 605 |
| 結束頁: | 610 |
| Appears in Collections: | Conferences Paper |
- Unified functional decomposition via encoding for FPGA technology mapping / Jiang, JH;Jou, JY;Huang, JD
- Compatible class encoding in hyper-function decomposition for FPGA synthesis / Jiang, JHR;Jou, JY;Huang, JD
- ALTO: An iterative area/performance tradeoff algorithm for LUT-based FPGA technology mapping / Huang, JD;Jou, JY;Shen, WZ
- A variable partitioning algorithm of BDD for FPGA technology mapping / Jiang, JH;Jou, JY;Huang, JD;Wei, JS
- LOGIC SYNTHESIS FOR FIELD-PROGRAMMABLE GATE ARRAYS / HWANG, TT;OWENS, RM;IRWIN, MJ;WANG, KH
- Technology mapping for FPGAs with composite logic block architectures / Chuang, HH;Shung, CB
- Technology mapping for FPGAs with composite logic block architectures / Chuang, HH;Shung, CB
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