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dc.contributor.authorWang, Kuan-Tien_US
dc.contributor.authorHsueh, Fang-Changen_US
dc.contributor.authorLu, Yu-Lunen_US
dc.contributor.authorChiang, Tsung-Yuen_US
dc.contributor.authorWu, Yi-Hongen_US
dc.contributor.authorLiao, Chia-Chunen_US
dc.contributor.authorYen, Li-Chenen_US
dc.contributor.authorChao, Tien-Shengen_US
dc.date.accessioned2014-12-08T15:28:22Z-
dc.date.available2014-12-08T15:28:22Z-
dc.date.issued2012-06-01en_US
dc.identifier.issn0741-3106en_US
dc.identifier.urihttp://dx.doi.org/10.1109/LED.2012.2192090en_US
dc.identifier.urihttp://hdl.handle.net/11536/20520-
dc.description.abstractThis letter is the first to successfully demonstrate the 2-bit/cell wrapped-selected-gate (WSG) SONOS thin-film transistor (TFT) memory using source-side injection (SSI). Because of the higher programming efficiency of SSI, a memory window of approximately 3 V can be easily achieved in 10 mu s and 30 ms for the program and erase modes, respectively. In addition, we performed an excellent 2-bit/cell distinguish margin for 3-V memory window in WSG-SONOS TFT memory. The optimal reliability of the endurance and data retention tests can be executed by adjusting the applied voltage appropriately.en_US
dc.language.isoen_USen_US
dc.subjectSource-side injection (SSI)en_US
dc.subjectthin-film transistor memoryen_US
dc.subjecttwo-bit/cellen_US
dc.subjectwrapped-selected-gate (WSG)-SONOSen_US
dc.titleNovel 2-Bit/Cell Wrapped-Select-Gate SONOS TFT Memory Using Source-Side Injection for NOR-Type Flash Arrayen_US
dc.typeArticleen_US
dc.identifier.doi10.1109/LED.2012.2192090en_US
dc.identifier.journalIEEE ELECTRON DEVICE LETTERSen_US
dc.citation.volume33en_US
dc.citation.issue6en_US
dc.citation.spage839en_US
dc.citation.epage841en_US
dc.contributor.department電子物理學系zh_TW
dc.contributor.departmentDepartment of Electrophysicsen_US
dc.identifier.wosnumberWOS:000305835000033-
dc.citation.woscount0-
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