標題: Failure Analysis on Gate-Driven ESD Clamp Circuit after TLP Stresses of Different Voltage Steps in a 16-V CMOS Process
作者: Dai, Chia-Tsen
Chiu, Po-Yen
Ker, Ming-Dou
Tsai, Fu-Yi
Peng, Yan-Hua
Tsai, Chia-Ku
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
公開日期: 2012
摘要: The ESD robustness of gate-driven ESD clamp circuit in a 16-V CMOS process was investigated by the stresses of transmission line pulse (TLP), human-body-model ESD test, and machine-model (MM) ESD test. After TLP stresses of different voltage steps, the same ESD clamp circuit got different secondary breakdown currents (It2). In order to understand such unusual phenomenon, the failure analysis on the TLP-stressed ESD clamp circuits was performed to find the failure mechanism.
URI: http://hdl.handle.net/11536/20755
ISBN: 978-1-4673-0980-6
ISSN: 1946-1550
期刊: 2012 19TH IEEE INTERNATIONAL SYMPOSIUM ON THE PHYSICAL AND FAILURE ANALYSIS OF INTEGRATED CIRCUITS (IPFA)
Appears in Collections:Conferences Paper