標題: | TRANSCONDUCTANCE ENHANCEMENT DUE TO BACK BIAS FOR SUBMICRON NMOSFET |
作者: | GUO, JC CHANG, MC LU, CY HSU, CCH CHUNG, SSS 電子工程學系及電子研究所 Department of Electronics Engineering and Institute of Electronics |
公開日期: | 1-Feb-1995 |
摘要: | For the first time, a new phenomenon of transconductance enhancement due to back bias found in submicron MOSFET's is reported. A two-dimensional numerical simulation has been performed to investigate the origin of this observation. The enhancement of the channel potential gradient is verified to be the main reason responsible for this anomalous transconductance enhancement effect. Moderate channel doping concentrations (5 x 10(16) similar to 5 x 10(17) cm(-3)), short channel lengths (submicron regime), and operation under small drain bias are three key conditions for the maximum transconductance enhancement due to the back bias to occur. A conventional linear I-V model, which employs an effective channel length defined by the source/drain metallurgical junctions and bias-independent source/drain extrinsic resistance is not able to predict such characteristics. |
URI: | http://dx.doi.org/10.1109/16.370067 http://hdl.handle.net/11536/2080 |
ISSN: | 0018-9383 |
DOI: | 10.1109/16.370067 |
期刊: | IEEE TRANSACTIONS ON ELECTRON DEVICES |
Volume: | 42 |
Issue: | 2 |
起始頁: | 288 |
結束頁: | 294 |
Appears in Collections: | Articles |
Files in This Item:
If it is a zip file, please download the file and unzip it, then open index.html in a browser to view the full text content.