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dc.contributor.authorFang, Bing-Nanen_US
dc.contributor.authorWu, Jieh-Tsorngen_US
dc.date.accessioned2014-12-08T15:29:24Z-
dc.date.available2014-12-08T15:29:24Z-
dc.date.issued2013-03-01en_US
dc.identifier.issn0018-9200en_US
dc.identifier.urihttp://dx.doi.org/10.1109/JSSC.2012.2233332en_US
dc.identifier.urihttp://hdl.handle.net/11536/21176-
dc.description.abstractA 10-bit pipelined ADC was fabricated using a 65 nm CMOS technology. To reduce power consumption, switching opamps are used. These switching opamps are designed to have a short turn-on time. Digital background calibration is employed to correct the A/D conversion error caused by the low dc gain of the opamps. The biasing voltages in each opamp are automatically generated using digital circuits. This bias scheme can maintain the settling behavior of the opamp against process-voltage-temperature variations. At 300 MS/s sampling rate, the ADC consumes 26.6 mW from a 1 V supply. Its measured DNL and INL are +0.52/-0.4 LSB and +0.99/-1.65 LSB respectively. Its measured SNDR and SFDR are 55.4 dB and 67.2 dB respectively. The chip active area is 0.36 mm(2).en_US
dc.language.isoen_USen_US
dc.subjectAnalog-to-digital conversionen_US
dc.subjectanalog digital conversionen_US
dc.subjectswitching circuitsen_US
dc.subjectcalibrationen_US
dc.subjectdigital background calibrationen_US
dc.subjectpipeline processingen_US
dc.subjectdigital bias generationen_US
dc.titleA 10-Bit 300-MS/s Pipelined ADC With Digital Calibration and Digital Bias Generationen_US
dc.typeArticleen_US
dc.identifier.doi10.1109/JSSC.2012.2233332en_US
dc.identifier.journalIEEE JOURNAL OF SOLID-STATE CIRCUITSen_US
dc.citation.volume48en_US
dc.citation.issue3en_US
dc.citation.spage670en_US
dc.citation.epage683en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000315523500004-
dc.citation.woscount5-
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