標題: A Low Quiescent Current Asynchronous Digital-LDO With PLL-Modulated Fast-DVS Power Management in 40 nm SoC for MIPS Performance Improvement
作者: Lee, Yu-Huei
Peng, Shen-Yu
Chiu, Chao-Chang
Wu, Alex Chun-Hsien
Chen, Ke-Horng
Lin, Ying-Hsi
Wang, Shih-Wei
Tsai, Tsung-Yen
Huang, Chen-Chih
Lee, Chao-Cheng
電控工程研究所
Institute of Electrical and Control Engineering
關鍵字: Asynchronous digital-LDO regulator;bidirectional asynchronous wave pipeline;dynamic voltage scaling;hybrid operation;million instructions per second performance;power conversion efficiency;power module;ripple-based control;switching regulator
公開日期: 1-Apr-2013
摘要: A low quiescent current asynchronous digital-LDO (D-LDO) regulator integrated with a phase-locked loop (PLL)-modulated switching regulator (SWR) that achieves the near-optimum power management supply for core processor in system-on-chip (SoC). The parallel connection of the asynchronous D-LDO regulator and the ripple-based control SWR can accomplish fast-DVS (F-DVS) operation as well as high power conversion efficiency. The asynchronous D-LDO regulator controlled by bidirectional asynchronous wave pipeline realizes the F-DVS operation, which guarantees high million instructions per second (MIPS) performance of the core processor under distinct tasks. The use of a ripple-based control SWR operating with a leading phase amplifier ensures fast response and stable operation without the need for large equivalent-series-resistance, thus reducing the output voltage ripple for the enhancement of supply quality. The fabricated chip occupies 1.04 mm(2) in 40 nm CMOS technology. Experimental results show that a 94% peak efficiency with a voltage tracking speed of 7.5 V/mu s as well as the improved MIPS performance by 5.6 times was achieved.
URI: http://dx.doi.org/10.1109/JSSC.2013.2237991
http://hdl.handle.net/11536/21510
ISSN: 0018-9200
DOI: 10.1109/JSSC.2013.2237991
期刊: IEEE JOURNAL OF SOLID-STATE CIRCUITS
Volume: 48
Issue: 4
起始頁: 1018
結束頁: 1030
Appears in Collections:Conferences Paper


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