標題: Design and Implementation of Dynamic Word-Line Pulse Write Margin Monitor for SRAM
作者: Wang, Shao-Cheng
Lin, Geng-Cing
Lin, Yi-Wei
Tsai, Ming-Chien
Chiu, Yi-Wei
Jou, Shyh-Jye
Chuang, Ching-Te
Lien, Nan-Chun
Shih, Wei-Chiang
Lee, Kuen-Di
Chu, Jyun-Kai
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
公開日期: 2012
摘要: We present an all-digital monitor structure to measure the Write Margin (WM) with dynamic Word-Line (WL) pulse for standard CMOS 6T SRAM. Ring oscillator and frequency divider based structures are used to generate wide range WL pulses (150ps similar to 32ns) with resolution of 50ps. The bit-line voltage is then successively stepped down for dynamic Write Margin characterization under given word-line pulse width. An improved Skitter based structure is employed to measure the WL pulse width with resolution of 10 similar to 20ps. Implementation of a 256Kb test chip in UMC 55nm Standard Performance (SP) CMOS technology is described.
URI: http://hdl.handle.net/11536/21523
ISBN: 978-1-4577-1728-4
期刊: 2012 IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS (APCCAS)
起始頁: 116
結束頁: 119
Appears in Collections:Conferences Paper