標題: A 10-Bit 200-MS/s Digitally-Calibrated Pipelined ADC Using Switching Opamps
作者: Fang, Bing-Nan
Wu, Jieh-Tsorng
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
公開日期: 2012
摘要: A 10-bit 200-MS/ s pipelined ADC was fabricated using a 90 nm CMOS technology. Switching opamps are used to save power. They are designed for high speed and fast turnon time. Digital background calibration is used to correct the conversion error caused by the low dc gain of the opamps. The ADC consumes 26 mW from a 1.1 V supply. Its measured DNL and INL are + 0.98/-0.81 LSB and + 1.4/-1.5 LSB respectively. Its measured SNDR and SFDR are 55 dB and 67.2 dB respectively. The chip active area is 0.69 mm(2).
URI: http://hdl.handle.net/11536/21561
ISBN: 978-1-4673-0219-7
ISSN: 0271-4302
期刊: 2012 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS 2012)
起始頁: 1042
結束頁: 1045
Appears in Collections:Conferences Paper