First Experimental Ge CMOS FinFETs Directly on SOI Substrate

標題:	First Experimental Ge CMOS FinFETs Directly on SOI Substrate
作者:	Chung, Cheng-Ting Chen, Che-Wei Lin, Jyun-Chih Wu, Che-Chen Chien, Chao-Hsin Luo, Guang-Li 電子工程學系及電子研究所 Department of Electronics Engineering and Institute of Electronics
公開日期:	2012
摘要:	High-performance Ge CMOS FinFETs directly on thin silicon on insulator (SOI) wafer are demonstrated. For the first time, NFET of L-channel = 120nm and Fin width=40nm with high I-on/I-off ratio (>10(5)), excellent drain induced barrier lowering (DIBL) (110mV/V) and subthreshold swing (S. S) (144mV/dec) has been shown. Both Ge n- and p-channel FinFETs with multi-fins have been achieved. Even the NFET of L-channel =90nm exhibits a pretty well on-off behavior after forming gas annealing.
URI:	http://hdl.handle.net/11536/21983
ISBN:	978-1-4673-4870-6
期刊:	2012 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM)
顯示於類別：	會議論文