標題: 2.4-GHz 7.4-mW 300-kHz Flicker-Noise-Corner Direct Conversion Receiver Using 0.18 mu m CMOS and Deep-N-Well NPN BJT
作者: Chang, Wei-Ling
Meng, Chin-Chun
Syu, Jin-Siang
Wang, Chia-Ling
Huang, Guo-Wei
電機工程學系
Department of Electrical and Computer Engineering
關鍵字: low power;low flicker noise;direct-conversion receiver;deep-n-well vertical-NPN bipolar junction transistor;Gilbert cell mixer;poly phase filter
公開日期: 2013
摘要: A low-power low-flicker-noise receiver is demonstrated using 0.18 mu m CMOS technology. Vertical-NPN bipolar junction transistors (BJTs) in standard CMOS process are used to substitute the mixer switching core and the input stage of subsequent IF VGA. Compared with the conventional CMOS mixer, the excellent flicker noise performance is obtained. As a result, the receiver achieves a 47 dB voltage gain at 2.4-GHz, and the noise figure is 9.6 dB at IF=100 kHz and 5.6 dB for IF>300 kHz. The total current consumption is 4.3 mA at 1.8 V supply voltage.
URI: http://hdl.handle.net/11536/22049
ISBN: 978-1-4673-2932-3
期刊: 2013 IEEE RADIO AND WIRELESS SYMPOSIUM (RWS)
起始頁: 223
結束頁: 225
Appears in Collections:Conferences Paper