標題: | 92% High Efficiency and Low Current Mismatch Interleaving Power Factor Correction Controller With Variable Sampling Slope and Automatic Loading Detection Techniques |
作者: | Su, Yi-Ping Chen, Chun-Yen Ni, Chia-Lung Kang, Yu-Chai Chen, Yi-Ting Tsai, Jen-Chieh Chen, Ke-Horng Wang, Shih-Ming Liang, Chao-Chiun Ho, Chang-An Yu, Tun-Hao 資訊工程學系 Department of Computer Science |
關鍵字: | Automatic loading detection (ALD);dual nondeadtime variable sampling slope (DNVSS);interleaving power factor correction (PFC) |
公開日期: | 1-Nov-2013 |
摘要: | This paper proposes the dual nondeadtime variable sampling slope technique to carry out precise phase sensing and suppress phase error in interleaving power factor correction (PFC) controller over a whole ac switching cycle for low current mismatch. Furthermore, the proposed automatic loading detection (ALD) technique can keep efficiency higher than 92% over a wide load range due to accurately controlling the ON/OFF of dual phases. The test circuit fabricated in the TSMC 0.5-mu m 800-V UHV process shows that the highly integrated interleaving PFC can deliver a high power of 180 W and a high efficiency of 95% at an output power of 180 W. |
URI: | http://dx.doi.org/10.1109/TPEL.2013.2240395 http://hdl.handle.net/11536/22084 |
ISSN: | 0885-8993 |
DOI: | 10.1109/TPEL.2013.2240395 |
期刊: | IEEE TRANSACTIONS ON POWER ELECTRONICS |
Volume: | 28 |
Issue: | 11 |
起始頁: | 5159 |
結束頁: | 5173 |
Appears in Collections: | Articles |
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