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dc.contributor.authorChen, Pin-Hanen_US
dc.contributor.authorWeng, Jian-Jiaen_US
dc.contributor.authorWang, Chung-Hsuanen_US
dc.contributor.authorChen, Po-Ningen_US
dc.date.accessioned2014-12-08T15:31:33Z-
dc.date.available2014-12-08T15:31:33Z-
dc.date.issued2013-05-01en_US
dc.identifier.issn1089-7798en_US
dc.identifier.urihttp://dx.doi.org/10.1109/LCOMM.2013.031913.130142en_US
dc.identifier.urihttp://hdl.handle.net/11536/22378-
dc.description.abstractIn this letter, we consider a concatenated BCH and QC-LDPC coding system for potential use of data protection on flash memory. Two issues are studied, and strategies to resolve them are proposed. First, in order to guarantee that the concatenated coding system is free from undesired error floor, we propose a strategy to select the outer BCH codes according to the error patterns of inner QC-LDPC code. We next present an iterative decoding algorithm between inner QC-LDPC and outer BCH codes to alleviate the performance degradation in the waterfall region due to code-concatenation rate loss. The two proposals jointly provide a feasible design for the concatenated BCH and QC-LDPC coding system. Simulations to verify the performance of the proposed concatenated coding system design are given at the end.en_US
dc.language.isoen_USen_US
dc.subjectConcatenated codingen_US
dc.subjectiterative decodingen_US
dc.subjectflash memoryen_US
dc.titleBCH Code Selection and Iterative Decoding for BCH and LDPC Concatenated Coding Systemen_US
dc.typeArticleen_US
dc.identifier.doi10.1109/LCOMM.2013.031913.130142en_US
dc.identifier.journalIEEE COMMUNICATIONS LETTERSen_US
dc.citation.volume17en_US
dc.citation.issue5en_US
dc.citation.spage980en_US
dc.citation.epage983en_US
dc.contributor.department電機資訊學士班zh_TW
dc.contributor.departmentUndergraduate Honors Program of Electrical Engineering and Computer Scienceen_US
dc.identifier.wosnumberWOS:000319706200042-
dc.citation.woscount1-
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