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dc.contributor.authorHo, Yingchiehen_US
dc.contributor.authorYang, Yu-Shengen_US
dc.contributor.authorChang, ChiaChien_US
dc.contributor.authorSu, Chauchinen_US
dc.date.accessioned2014-12-08T15:32:53Z-
dc.date.available2014-12-08T15:32:53Z-
dc.date.issued2013-11-01en_US
dc.identifier.issn0018-9200en_US
dc.identifier.urihttp://dx.doi.org/10.1109/JSSC.2013.2280409en_US
dc.identifier.urihttp://hdl.handle.net/11536/22937-
dc.description.abstractThis paper presents a near-threshold low-power all-digital PLL (ADPLL). It includes a 9-bit bootstrapped DCO (BDCO) to reduce supply voltage and power consumption, a weighted thermometer-controlled resistor network (WTRN) to achieve high linearity, and a 4-bit sigma-delta modulator to improve the resolution through dithering. The ADPLL is fabricated in a 90 nm SPRVT low-K CMOS process with a core area of 0.057 mm(2). The measured results demonstrate that the bootstrapped ring oscillator (BTRO) oscillates at 602 MHz under a supply of 0.5 V and consumes 49.1 mu W. The ADPLL operates at 480 MHz (48 MHz) with a power consumption of 78 mu W (2.4 mu W) under a supply voltage of 0.5 V (0.25 V).en_US
dc.language.isoen_USen_US
dc.subjectAll-digital phase-locked loop (ADPLL)en_US
dc.subjectbootstrapped circuiten_US
dc.subjectenergy-efficient designen_US
dc.subjectlow-poweren_US
dc.subjectlow-voltageen_US
dc.subjectnear-threshold circuiten_US
dc.titleA Near-Threshold 480 MHz 78 mu W All-Digital PLL With a Bootstrapped DCOen_US
dc.typeArticleen_US
dc.identifier.doi10.1109/JSSC.2013.2280409en_US
dc.identifier.journalIEEE JOURNAL OF SOLID-STATE CIRCUITSen_US
dc.citation.volume48en_US
dc.citation.issue11en_US
dc.citation.spage2805en_US
dc.citation.epage2814en_US
dc.contributor.department交大名義發表zh_TW
dc.contributor.department電機工程學系zh_TW
dc.contributor.departmentNational Chiao Tung Universityen_US
dc.contributor.departmentDepartment of Electrical and Computer Engineeringen_US
dc.identifier.wosnumberWOS:000326265100021-
dc.citation.woscount0-
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