完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Chen, Che-Wei | en_US |
dc.contributor.author | Chung, Cheng-Ting | en_US |
dc.contributor.author | Tzeng, Ju-Yuan | en_US |
dc.contributor.author | Chang, Pang-Sheng | en_US |
dc.contributor.author | Luo, Guang-Li | en_US |
dc.contributor.author | Chien, Chao-Hsin | en_US |
dc.date.accessioned | 2014-12-08T15:33:55Z | - |
dc.date.available | 2014-12-08T15:33:55Z | - |
dc.date.issued | 2014-01-01 | en_US |
dc.identifier.issn | 0741-3106 | en_US |
dc.identifier.uri | http://dx.doi.org/10.1109/LED.2013.2291394 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/23384 | - |
dc.description.abstract | In this letter, we demonstrate body-tied Ge tri-gate junctionless (JL) p-channel MOSFETs directly on Si. Our tri-gate JL-PFET exhibits higher current than the conventional inversion-mode transistor through in-situ heavily doped technique and trimming down Ge fin width. We show that the JL-PFET with tri-gate structure has excellent I-ON/I-OFF ratio and good short channel effect control on the channel potential. The current ratio is of similar to 6 x 10(3) (I-D) at V-DS = -0.1 V, V-GS = -3, and 0 V. The relatively low OFF-current is of 6 nA/ mu m at V-DS = -0.1 V and V-GS = 0 V. The subthreshold swing of 203 mV/decade and drain induced barrier lowering of 220 mV/V are reported at L-G = 120 nm. | en_US |
dc.language.iso | en_US | en_US |
dc.subject | Junctionless | en_US |
dc.subject | tri-gate | en_US |
dc.subject | germanium | en_US |
dc.subject | body-tied | en_US |
dc.subject | in-situ heavily doped | en_US |
dc.title | Body-Tied Germanium Tri-Gate Junctionless PMOSFET With In-Situ Boron Doped Channel | en_US |
dc.type | Article | en_US |
dc.identifier.doi | 10.1109/LED.2013.2291394 | en_US |
dc.identifier.journal | IEEE ELECTRON DEVICE LETTERS | en_US |
dc.citation.volume | 35 | en_US |
dc.citation.issue | 1 | en_US |
dc.citation.spage | 12 | en_US |
dc.citation.epage | 14 | en_US |
dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
dc.identifier.wosnumber | WOS:000329061300004 | - |
dc.citation.woscount | 0 | - |
顯示於類別: | 期刊論文 |