完整後設資料紀錄
DC 欄位語言
dc.contributor.authorChen, Che-Weien_US
dc.contributor.authorChung, Cheng-Tingen_US
dc.contributor.authorTzeng, Ju-Yuanen_US
dc.contributor.authorChang, Pang-Shengen_US
dc.contributor.authorLuo, Guang-Lien_US
dc.contributor.authorChien, Chao-Hsinen_US
dc.date.accessioned2014-12-08T15:33:55Z-
dc.date.available2014-12-08T15:33:55Z-
dc.date.issued2014-01-01en_US
dc.identifier.issn0741-3106en_US
dc.identifier.urihttp://dx.doi.org/10.1109/LED.2013.2291394en_US
dc.identifier.urihttp://hdl.handle.net/11536/23384-
dc.description.abstractIn this letter, we demonstrate body-tied Ge tri-gate junctionless (JL) p-channel MOSFETs directly on Si. Our tri-gate JL-PFET exhibits higher current than the conventional inversion-mode transistor through in-situ heavily doped technique and trimming down Ge fin width. We show that the JL-PFET with tri-gate structure has excellent I-ON/I-OFF ratio and good short channel effect control on the channel potential. The current ratio is of similar to 6 x 10(3) (I-D) at V-DS = -0.1 V, V-GS = -3, and 0 V. The relatively low OFF-current is of 6 nA/ mu m at V-DS = -0.1 V and V-GS = 0 V. The subthreshold swing of 203 mV/decade and drain induced barrier lowering of 220 mV/V are reported at L-G = 120 nm.en_US
dc.language.isoen_USen_US
dc.subjectJunctionlessen_US
dc.subjecttri-gateen_US
dc.subjectgermaniumen_US
dc.subjectbody-tieden_US
dc.subjectin-situ heavily dopeden_US
dc.titleBody-Tied Germanium Tri-Gate Junctionless PMOSFET With In-Situ Boron Doped Channelen_US
dc.typeArticleen_US
dc.identifier.doi10.1109/LED.2013.2291394en_US
dc.identifier.journalIEEE ELECTRON DEVICE LETTERSen_US
dc.citation.volume35en_US
dc.citation.issue1en_US
dc.citation.spage12en_US
dc.citation.epage14en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000329061300004-
dc.citation.woscount0-
顯示於類別:期刊論文


文件中的檔案:

  1. 000329061300004.pdf

若為 zip 檔案,請下載檔案解壓縮後,用瀏覽器開啟資料夾中的 index.html 瀏覽全文。