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dc.contributor.authorLiu, Wei-Changen_US
dc.contributor.authorYeh, Fu-Chunen_US
dc.contributor.authorWei, Ting-Chenen_US
dc.contributor.authorHuang, Ya-Shiueen_US
dc.contributor.authorLiu, Tai-Yangen_US
dc.contributor.authorHuang, Shen-Juien_US
dc.contributor.authorChan, Ching-Daen_US
dc.contributor.authorJou, Shyh-Jyeen_US
dc.contributor.authorChen, Sau-Geeen_US
dc.date.accessioned2014-12-08T15:35:45Z-
dc.date.available2014-12-08T15:35:45Z-
dc.date.issued2013en_US
dc.identifier.isbn978-1-4673-5762-3; 978-1-4673-5760-9en_US
dc.identifier.issn0271-4302en_US
dc.identifier.urihttp://hdl.handle.net/11536/24134-
dc.description.abstractIn this paper, an 8X-parallelism digital baseband receiver is proposed for IEEE 802.15.3c application. The baseband receiver consists of all-digital synchronization, radix-16 FFT and LS-LMS equalizer modules. It supports SC and HSI dual-mode in IEEE 802.15.3c with single hardware for area efficiency. The chip is implemented with 65 nm 1P9M process. The fabricated area is 12.96 mm(2) with 3463 K gate counts. The post-layout verification shows the throughput rate under QPSK modulation achieves 3.52 Gb/s and 5.28 Gb/s for SC mode (220 MHz) and HSI mode (330 MHz), respectively.en_US
dc.language.isoen_USen_US
dc.titleA SC/HSI Dual-Mode Baseband Receiver with Frequency-Domain Equalizer for IEEE 802.15.3cen_US
dc.typeProceedings Paperen_US
dc.identifier.journal2013 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS)en_US
dc.citation.spage793en_US
dc.citation.epage796en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000332006801012-
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