完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Liu, Wei-Chang | en_US |
dc.contributor.author | Yeh, Fu-Chun | en_US |
dc.contributor.author | Wei, Ting-Chen | en_US |
dc.contributor.author | Huang, Ya-Shiue | en_US |
dc.contributor.author | Liu, Tai-Yang | en_US |
dc.contributor.author | Huang, Shen-Jui | en_US |
dc.contributor.author | Chan, Ching-Da | en_US |
dc.contributor.author | Jou, Shyh-Jye | en_US |
dc.contributor.author | Chen, Sau-Gee | en_US |
dc.date.accessioned | 2014-12-08T15:35:45Z | - |
dc.date.available | 2014-12-08T15:35:45Z | - |
dc.date.issued | 2013 | en_US |
dc.identifier.isbn | 978-1-4673-5762-3; 978-1-4673-5760-9 | en_US |
dc.identifier.issn | 0271-4302 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/24134 | - |
dc.description.abstract | In this paper, an 8X-parallelism digital baseband receiver is proposed for IEEE 802.15.3c application. The baseband receiver consists of all-digital synchronization, radix-16 FFT and LS-LMS equalizer modules. It supports SC and HSI dual-mode in IEEE 802.15.3c with single hardware for area efficiency. The chip is implemented with 65 nm 1P9M process. The fabricated area is 12.96 mm(2) with 3463 K gate counts. The post-layout verification shows the throughput rate under QPSK modulation achieves 3.52 Gb/s and 5.28 Gb/s for SC mode (220 MHz) and HSI mode (330 MHz), respectively. | en_US |
dc.language.iso | en_US | en_US |
dc.title | A SC/HSI Dual-Mode Baseband Receiver with Frequency-Domain Equalizer for IEEE 802.15.3c | en_US |
dc.type | Proceedings Paper | en_US |
dc.identifier.journal | 2013 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS) | en_US |
dc.citation.spage | 793 | en_US |
dc.citation.epage | 796 | en_US |
dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
dc.identifier.wosnumber | WOS:000332006801012 | - |
顯示於類別: | 會議論文 |