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dc.contributor.authorKer, MDen_US
dc.contributor.authorHsu, HCen_US
dc.date.accessioned2014-12-08T15:36:14Z-
dc.date.available2014-12-08T15:36:14Z-
dc.date.issued2005-01-01en_US
dc.identifier.issn1057-7122en_US
dc.identifier.urihttp://dx.doi.org/10.1109/TCSI.2004.840105en_US
dc.identifier.urihttp://hdl.handle.net/11536/24569-
dc.description.abstractA substrate-triggered technique is proposed to improve the electrostatic discharge (ESD) robustness of a stacked-nMOS device in the mixed-voltage I/O circuit. The substrate-triggered technique can further lower the trigger voltage of a stacked-nMOS device to ensure effective ESD protection for mixed-voltage I/O circuits. The proposed ESD protection circuit with substrate- triggered design for a 2.5-V/3.3-V-tolerant mixed-voltage I/O circuit has been fabricated and verified in a 0.25-mum salicided CMOS process. The substrate-triggered circuit for a mixed-voltage I/O buffer to meet the desired circuit application in different CMOS processes can be easily adjusted by using HSPICE simulation. Experimental results have confirmed that the human-body-model (HBM) ESD robustness of a mixed-voltage I/O circuit can be increased similar to60% by this substrate-triggered design.en_US
dc.language.isoen_USen_US
dc.subjectelectrostatic discharge (ESD)en_US
dc.subjectstacked nMOSen_US
dc.subjectsubstrate-triggered techniqueen_US
dc.subjectmixed-voltage I/Oen_US
dc.titleESD protection design for mixed-voltage I/O buffer with substrate-triggered circuiten_US
dc.typeArticleen_US
dc.identifier.doi10.1109/TCSI.2004.840105en_US
dc.identifier.journalIEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERSen_US
dc.citation.volume52en_US
dc.citation.issue1en_US
dc.citation.spage44en_US
dc.citation.epage53en_US
dc.contributor.department電機學院zh_TW
dc.contributor.departmentCollege of Electrical and Computer Engineeringen_US
dc.identifier.wosnumberWOS:000226247800005-
dc.citation.woscount7-
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