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dc.contributor.authorSheu, YMen_US
dc.contributor.authorYang, SJen_US
dc.contributor.authorWang, CCen_US
dc.contributor.authorChang, CSen_US
dc.contributor.authorHuang, LPen_US
dc.contributor.authorHuang, TYen_US
dc.contributor.authorChen, MJen_US
dc.contributor.authorDiaz, CHen_US
dc.date.accessioned2014-12-08T15:36:15Z-
dc.date.available2014-12-08T15:36:15Z-
dc.date.issued2005-01-01en_US
dc.identifier.issn0018-9383en_US
dc.identifier.urihttp://dx.doi.org/10.1109/TED.2004.841286en_US
dc.identifier.urihttp://hdl.handle.net/11536/24580-
dc.description.abstractThe effect of shallow trench isolation mechanical stress on MOSFET dopant diffusion has become significant, and affects device behavior for sub-100-nm technologies. This paper presents a stress-dependent dopant diffusion model and demonstrates its capability to reflect experimental results for a state-of-the-art logic CMOS technology. The proposed stress-dependent dopant diffusion model is shown to successfully reproduce device characteristics covering a wide range of active area sizes, gate lengths, and device operating conditions.en_US
dc.language.isoen_USen_US
dc.subjectdopant diffusionen_US
dc.subjectmechanical stressen_US
dc.subjectmodelingen_US
dc.subjectMOSFETen_US
dc.subjectshallow trench isolation (STI)en_US
dc.subjectsimulationen_US
dc.subjectstrainen_US
dc.titleModeling mechanical stress effect on dopant diffusion in scaled MOSFETsen_US
dc.typeArticleen_US
dc.identifier.doi10.1109/TED.2004.841286en_US
dc.identifier.journalIEEE TRANSACTIONS ON ELECTRON DEVICESen_US
dc.citation.volume52en_US
dc.citation.issue1en_US
dc.citation.spage30en_US
dc.citation.epage38en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000225915000006-
dc.citation.woscount45-
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