完整後設資料紀錄
DC 欄位語言
dc.contributor.authorCheng, Y. L.en_US
dc.contributor.authorChang, Y. M.en_US
dc.contributor.authorLeu, Jihperngen_US
dc.contributor.authorBo, T. C.en_US
dc.contributor.authorWang, Y. L.en_US
dc.date.accessioned2014-12-08T15:36:28Z-
dc.date.available2014-12-08T15:36:28Z-
dc.date.issued2014-10-05en_US
dc.identifier.issn0167-9317en_US
dc.identifier.urihttp://dx.doi.org/10.1016/j.mee.2014.05.036en_US
dc.identifier.urihttp://hdl.handle.net/11536/24802-
dc.description.abstractThis study demonstrates that the electromigration (EM) behavior of dual damascene Cu lines is strongly affected by the layout which surrounded the tested EM lines, especially for Cu line below 0.10 mu m used for 40 nm or below technologies. The Cu EM lifetime declines as the number of local dummy lines increase, and the global dummy line density increases with the width of the Cu line below 0.063 mu m. This work presents mechanisms of layout effects that explain the EM characteristics and can be exploited to improve the layout effect. Therefore, not only the stressed Cu line structures, but also the surrounding layouts must to be considered in assessing EM reliability of a real IC circuit in 40 nm or below technology. (C) 2014 Elsevier B.V. All rights reserved.en_US
dc.language.isoen_USen_US
dc.subjectElectromigrationen_US
dc.subjectInterconnectsen_US
dc.subjectCopperen_US
dc.subjectLayouten_US
dc.titleEffect of layout on electromigration characteristics in copper dual damascene interconnectsen_US
dc.typeArticleen_US
dc.identifier.doi10.1016/j.mee.2014.05.036en_US
dc.identifier.journalMICROELECTRONIC ENGINEERINGen_US
dc.citation.volume128en_US
dc.citation.issueen_US
dc.citation.spage19en_US
dc.citation.epage23en_US
dc.contributor.department材料科學與工程學系zh_TW
dc.contributor.departmentDepartment of Materials Science and Engineeringen_US
dc.identifier.wosnumberWOS:000340221500004-
dc.citation.woscount0-
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