標題: An Efficient VLSI Implementation of On-line Recursive ICA Processor for Real-time Multi-channel EEG Signal Separation
作者: Shih, Wei-Yeh
Liao, Jui-Chieh
Huang, Kuan-Ju
Fang, Wai-Chi
Cauwenberghs, Gert
Jung, Tzyy-Ping
交大名義發表
電機工程學系
National Chiao Tung University
Department of Electrical and Computer Engineering
公開日期: 2013
摘要: This paper presents an efficient VLSI implementation of on-line recursive ICA (ORICA) processor for real-time multi-channel EEG signal separation. The proposed design contains a system control unit, a whitening unit, a singular value decomposition unit, a floating matrix multiply unit and, and an ORICA weight training unit. Because the input sample rate of the ORICA processor is 128 Hz, the ORICA processor should produce independent components before the next sample is input in 1/128 s. Under the timing constraints of commutating multi-channel ORICA in real time, the design of the ORICA processor is a mixed architecture, which is designed as different hardware parallelism according to the complexity of processing units. The shared arithmetic processing unit and shared register can reduce hardware complexity and power consumption. The proposed design is implemented used TSMC 90nm CMOS technology with 8-channel EEG processing in 128 Hz sample rate of raw data and consumes 2.827 mW at 50 MHz clock rate. The performance of the proposed design is also shown to reach 0.0078125 s latency after each EEG sample time, and the average correlation coefficient between the original source signals and extracted ORICA signals for each 1s frame is 0.9763.
URI: http://hdl.handle.net/11536/25140
ISBN: 978-1-4577-0216-7
ISSN: 1557-170X
期刊: 2013 35TH ANNUAL INTERNATIONAL CONFERENCE OF THE IEEE ENGINEERING IN MEDICINE AND BIOLOGY SOCIETY (EMBC)
起始頁: 6808
結束頁: 6811
Appears in Collections:Conferences Paper