完整後設資料紀錄
DC 欄位語言
dc.contributor.authorChu, Ching-Yunen_US
dc.contributor.authorWang, Yu-Jiuen_US
dc.date.accessioned2014-12-08T15:36:57Z-
dc.date.available2014-12-08T15:36:57Z-
dc.date.issued2014-10-01en_US
dc.identifier.issn1549-7747en_US
dc.identifier.urihttp://dx.doi.org/10.1109/TCSII.2014.2345296en_US
dc.identifier.urihttp://hdl.handle.net/11536/25358-
dc.description.abstractThis brief presents a new process, voltage, and temperature (PVT)-independent constant-G(m) bias technique for any I-out(V-in)-monotonic convex (or concave) transconductors. In this brief, the conventional constant-g(m) biasing is formulated into an analog computation process that calculates the constant-G(m) bias voltage V-0 from an input current. An analog computer measures the effective G(m) from two matched transconductors and converges it to the inverse of a precision resistance by adjusting V-0. Through this, a well-defined large-signal constant-G(m) bias voltage can be found. The proposed technique eliminates the power-law or exponential-law assumptions on the I-out(V-in) characteristics in a conventional design. An interpolation calculation follows to find the optimal small-signal constant-g(m) bias voltage V-out. The fundamental limitations of the proposed technique are the required monotonicity and convexity (or concavity) of the transconductor\'s I-out(V-in). Error sources include mismatches of paired devices and the input offset voltage and open-loop gain of the operation amplifier (OpAmp). These errors are analyzed in detail in this brief. Biasing circuits based on different transistor types are designed using the Taiwan Semiconductor Manufacturing Company (TSMC) 65-nm CMOS process. Computer simulations show that the proposed biasing circuitry can achieve +/- 0.22% g(m) variations from -60 degrees C to 130 degrees C.en_US
dc.language.isoen_USen_US
dc.titleA PVT-Independent Constant-G(m) Bias Technique Based on Analog Computationen_US
dc.typeArticleen_US
dc.identifier.doi10.1109/TCSII.2014.2345296en_US
dc.identifier.journalIEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFSen_US
dc.citation.volume61en_US
dc.citation.issue10en_US
dc.citation.spage768en_US
dc.citation.epage772en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000343320500008-
dc.citation.woscount0-
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