標題: A Real-Time High-Throughput LDPC Decoder for IEEE 802.3an Standard
作者: Hung, Jui-Hui
Kao, Li-Wei
Chen, Sau-Gee
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
關鍵字: channel coding;ldpc;hardware design;802.3an standard
公開日期: 2010
摘要: The existing LDPC decoders are mostly based on the belief-propagation (BP) algorithms, due to good BER performances. However, they demand large chip areas. This paper proposes a high-throughput LDPC decoder based on the bit-flipping algorithms, for the (2048, 1723) RS-LDPC code adopted in the IEEE 802.3an standard. High decoding performances and low iteration numbers are achieved by introducing a strategy of flipping low-correlation bits and an additional syndrome vote scheme. As a result, the decoding performance is very close to the most popular BP-based min-sum algorithm (MSA) but with much lower computational complexity. Besides, the decoder achieves high hardware utilization with real-time processing capability. Synthesized with UMC 90nm process, the decoder chip area, throughput and average power dissipation are 1.42M gates, 16Gbps and 368mW, respectively, at 500MHz clock rate. Compared with existing BP-based designs, it has much smaller chip area and lower power dissipation, with comparable performances.
URI: http://hdl.handle.net/11536/25787
ISBN: 978-1-4244-2519-8
ISSN: 1550-2252
期刊: 2010 IEEE 71ST VEHICULAR TECHNOLOGY CONFERENCE
Appears in Collections:Conferences Paper