完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | CHEN, BY | en_US |
dc.contributor.author | LEE, CL | en_US |
dc.date.accessioned | 2014-12-08T15:04:06Z | - |
dc.date.available | 2014-12-08T15:04:06Z | - |
dc.date.issued | 1994-03-01 | en_US |
dc.identifier.issn | 0278-0070 | en_US |
dc.identifier.uri | http://dx.doi.org/10.1109/43.265678 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/2609 | - |
dc.description.abstract | In this paper, a fast universal test set (UTS) generation algorithm for multi-output functions is presented. The algorithm first generates the UTS for single-output functions by directly Shannon-expanding and complementing the function. This significantly reduces the time complexity and the usage of temporary memory. Also, it stores tests in test cubes to save the size of memory for test storing. Two-six orders of magnitude in computation efficiency improvement and 1-1800 fold for memory saving over the conventional method are achieved. It then merges the generated test cubes for each single-output function into a set of mutually disjoint test cubes to be the UTS for a multi-output function by employing a new compaction technique. The size of UTS thus obtained is 1-20 times smaller than that of UTS without compaction. | en_US |
dc.language.iso | en_US | en_US |
dc.title | A COMPLEMENT-BASED FAST ALGORITHM TO GENERATE UNIVERSAL TEST SETS FOR MULTIOUTPUT FUNCTIONS | en_US |
dc.type | Article | en_US |
dc.identifier.doi | 10.1109/43.265678 | en_US |
dc.identifier.journal | IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS | en_US |
dc.citation.volume | 13 | en_US |
dc.citation.issue | 3 | en_US |
dc.citation.spage | 370 | en_US |
dc.citation.epage | 377 | en_US |
dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
dc.identifier.wosnumber | WOS:A1994MZ93600009 | - |
dc.citation.woscount | 4 | - |
顯示於類別: | 期刊論文 |