通用測試集的產生及應用

Abstract

本論文針對通用測試集的產生及應用，提出一些新的演算法及應用領域， 整理如下：一、針對不同的障礙模型，提出用來產 生組合邏輯電路區塊 的通用測試集的快速演算法。這些演算法利用雪諾展開及求補函數的方式 來產生通用測試集，完全消除傳統用真值表展開的方法所產生的問題。不 但大大地降低產生通用測試集的計算複雜度，並且節省大量暫存記憶體的 使用。另外，這些演算法以「立方體」的方式來儲存測試圖樣，因此節省 許多儲存測試圖樣的空間。為了得到多輸出函數的通用測試集，我們也提 出一個新的方法來壓縮輸出與輸出之間的通用測試集。二、利用前面產生 出來的通用測試集，我們提出一組延遲障礙的通用測試集，這組測試集可 以測到存在於一個函數的任一個「Unate G- ate Network」 實現電路的 所有可測試閘延遲障礙。三、利用通用測試集，我們亦提出一個新的設計 驗證方法。我們導出一些定理證明這個設計驗證方法幾乎可以驗證「 Unate Gate Network」實現電路的所有設計錯誤。實驗結果顯示，此設計 驗證方法速度快並且省記憶體。 In the dissertation, the generation and application of universal test sets (UTS) are studied and discussed. (1) We propose fast algorithms to generate the UTS for different fault models for combinational function blocks. The algorithms generate the UTS by Shannon expanding and complementing the function instead of the conventional truth table enumerating. This significantly reduces the time complexity and the usage of temporary memory and memroy for test-storing. To obtain the UTS for multi-output functions, a new compaction method is also employed to obtain the UTS for the multi-output functions. (2) By applying the UTS to delay fault testing, we propose a universal delay fault test set, which can detect all the detectable gate delay faults in any "unate gate network" realization of the function. (3) Based on the UTS, a new design verification approach is proposed. Theorem are presented to show that the approach can verify almost all the design errors in any "unate gate network" circuit realization under verification. Experimental results show that the design verification approach is time efficient and memory saving.