A CMOS 8-Bit 1.6-GS/s DAC With Digital Random Return-to-Zero

doi:10.1109/TCSII.2010.2092823

完整後設資料紀錄

DC 欄位	值	語言
dc.contributor.author	Tseng, Wei-Hsin	en_US
dc.contributor.author	Wu, Jieh-Tsorng	en_US
dc.contributor.author	Chu, Yung-Cheng	en_US
dc.date.accessioned	2014-12-08T15:38:04Z	-
dc.date.available	2014-12-08T15:38:04Z	-
dc.date.issued	2011-01-01	en_US
dc.identifier.issn	1549-7747	en_US
dc.identifier.uri	http://dx.doi.org/10.1109/TCSII.2010.2092823	en_US
dc.identifier.uri	http://hdl.handle.net/11536/26111	-
dc.description.abstract	A digital random return-to-zero technique is presented to improve the dynamic performance of current-steering digital-to-analog converters (DACs). To demonstrate the proposed technique, a CMOS 8-bit 1.6-GS/s DAC was fabricated in a 90-nm CMOS technology. The DAC achieves a spurious-free dynamic range better than 60 dB for a sine-wave input up to 460 MHz and better than 55 dB up to 800 MHz. The DAC consumes 90 mW of power.	en_US
dc.language.iso	en_US	en_US
dc.subject	Current steering	en_US
dc.subject	digital-to-analog converter (DAC)	en_US
dc.subject	digital random return-to-zero (DRRZ)	en_US
dc.subject	return-to-zero (RZ)	en_US
dc.title	A CMOS 8-Bit 1.6-GS/s DAC With Digital Random Return-to-Zero	en_US
dc.type	Article	en_US
dc.identifier.doi	10.1109/TCSII.2010.2092823	en_US
dc.identifier.journal	IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS	en_US
dc.citation.volume	58	en_US
dc.citation.issue	1	en_US
dc.citation.spage	1	en_US
dc.citation.epage	5	en_US
dc.contributor.department	電子工程學系及電子研究所	zh_TW
dc.contributor.department	Department of Electronics Engineering and Institute of Electronics	en_US
dc.identifier.wosnumber	WOS:000286519800001	-
dc.citation.woscount	7	-
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