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dc.contributor.authorWang, Chang-Tzuen_US
dc.contributor.authorKer, Ming-Douen_US
dc.date.accessioned2014-12-08T15:38:25Z-
dc.date.available2014-12-08T15:38:25Z-
dc.date.issued2010-12-01en_US
dc.identifier.issn0018-9383en_US
dc.identifier.urihttp://dx.doi.org/10.1109/TED.2010.2079530en_US
dc.identifier.urihttp://hdl.handle.net/11536/26301-
dc.description.abstractAn electrostatic discharge (ESD) protection design for smart power applications with lateral double-diffused MOS (LDMOS) transistors is investigated. With the gate-driven and substrate-triggered circuit techniques, the n-channel LDMOS can be quickly turned on to protect the output drivers during an ESD stress event. The proposed gate-driven and substrate-triggered ESD protection circuits have been successfully verified in a 0.35-mu m 5 V/40 V bipolar CMOS DMOS (BCD) process, which can sustain ESD voltages of 4 kV in human-body-model (HBM) and 275 V in machine-model (MM) ESD tests. In addition, the power-rail ESD protection design can also be achieved with a stacked structure to protect 40-V power pins without a latchup issue in the smart power integrated circuits.en_US
dc.language.isoen_USen_US
dc.subjectBipolar CMOS DMOS (BCD) processen_US
dc.subjectelectrostatic discharge (ESD)en_US
dc.subjectESD protectionen_US
dc.subjectlatchupen_US
dc.titleESD Protection Design With Lateral DMOS Transistor in 40-V BCD Technologyen_US
dc.typeArticleen_US
dc.identifier.doi10.1109/TED.2010.2079530en_US
dc.identifier.journalIEEE TRANSACTIONS ON ELECTRON DEVICESen_US
dc.citation.volume57en_US
dc.citation.issue12en_US
dc.citation.spage3395en_US
dc.citation.epage3404en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000284417700022-
dc.citation.woscount8-
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