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dc.contributor.authorKer, MDen_US
dc.contributor.authorChen, ZPen_US
dc.date.accessioned2014-12-08T15:38:26Z-
dc.date.available2014-12-08T15:38:26Z-
dc.date.issued2004-10-01en_US
dc.identifier.issn0018-9383en_US
dc.identifier.urihttp://dx.doi.org/10.1109/TED.2004.834904en_US
dc.identifier.urihttp://hdl.handle.net/11536/26326-
dc.description.abstractA dynamic-holding-voltage silicon-controlled rectifier (DHVSCR) device is proposed and verified in a 0.25-mum/2.5-V salicided CMOS process. In the DHVSCR device structure, the control nMOS and pMOS transistors are directly embedded in SCR device structure. The proposed DHVSCR device has the characteristics of tunable holding voltage and holding current by changing the gate voltage of embedded nMOS and pMOS. Under normal circuit operating condition, the DHVSCR has a holding voltage higher than the supply voltage without causing a latch-up issue. Under an electrostatic discharge (ESD) stress condition, the DHVSCR has a lower holding voltage to effectively clamp the overshooting ESD voltage. From the experimental results, the DHVSCR with a device width of 50 mum can sustain a human-body-model ESD level of 5.6 kV.en_US
dc.language.isoen_USen_US
dc.subjectelectrostatic discharge (ESD)en_US
dc.subjectholding voltageen_US
dc.subjectlatch-upen_US
dc.subjectsilicon-controlled rectifier (SCR)en_US
dc.titleSCR device with dynamic holding voltage for on-chip ESD protection in a 0.25-mu m fully salicided CMOS processen_US
dc.typeArticleen_US
dc.identifier.doi10.1109/TED.2004.834904en_US
dc.identifier.journalIEEE TRANSACTIONS ON ELECTRON DEVICESen_US
dc.citation.volume51en_US
dc.citation.issue10en_US
dc.citation.spage1731en_US
dc.citation.epage1733en_US
dc.contributor.department電機學院zh_TW
dc.contributor.departmentCollege of Electrical and Computer Engineeringen_US
dc.identifier.wosnumberWOS:000224104700026-
dc.citation.woscount8-
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