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dc.contributor.authorLin, Chen-Yangen_US
dc.contributor.authorWong, Cheng-Chien_US
dc.contributor.authorChang, Hsie-Chiaen_US
dc.date.accessioned2014-12-08T15:38:32Z-
dc.date.available2014-12-08T15:38:32Z-
dc.date.issued2010en_US
dc.identifier.isbn978-1-4244-5309-2en_US
dc.identifier.issn0271-4302en_US
dc.identifier.urihttp://hdl.handle.net/11536/26387-
dc.description.abstractTo increase channel efficiency for high throughput systems, the high code-rate schemes are usually required. However, conventional turbo decoders in high code-rate usually apply high radix trellis structure, and the complexity of the trellis increases exponentially according to the code-rate. In this paper, the reciprocal dual trellis is applied to reduce the trellis complexity and a multiple code-rate turbo decoder is proposed. A sign magnitude representation is also introduced to lower the hardware complexity. The puncturing methodology is applied to WCDMA system as a case study of high code-rate turbo codes, and the investigated code-rates are 1/3, 1/2, 2/3, and 4/5. The simulation results are also shown in this paper. Fabricated with CMOS 90nm process, the proposed decoder containing 370K logic gates and 58kb storage units can achieve 101Mb/s with 80mW at code-rate 4/5.en_US
dc.language.isoen_USen_US
dc.titleA Multiple Code-Rate Turbo Decoder Based on Reciprocal Dual Trellis Architectureen_US
dc.typeArticleen_US
dc.identifier.journal2010 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMSen_US
dc.citation.spage1496en_US
dc.citation.epage1499en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000287216001187-
Appears in Collections:Conferences Paper