Design on ESD protection scheme for IC with power-down-mode operation

Abstract

This paper presents a new electrostatic discharge (ESD) protection scheme for IC with power-down-mode operation. Adding a VDD ESD bus line and diodes into the proposed ESD protection scheme can block the leakage current from I/O pin to VDD power line and avoid malfunction during power-down operation. The whole-chip ESD protection design can be achieved by insertion of ESD clamp circuits between VSS power line and both the VDD power line and VDD ESD bus line. Experiment results show that the human-body model (HBM) ESD level of this new scheme can be greater than 7.5 kV in a 0.35-mum silicided CMOS process.